Chris's Wiki :: blog/tech/TwoRISCStories Commentshttps://utcc.utoronto.ca/~cks/space/blog/tech/TwoRISCStories?atomcommentsDWiki2023-02-04T22:27:59ZRecent comments in Chris's Wiki :: blog/tech/TwoRISCStories.By crest on /blog/tech/TwoRISCStoriestag:CSpace:blog/tech/TwoRISCStories:399c3bb19c32a4a4c6d125d83447f2540c3b51bccrest<div class="wikitext"><p>The problem with Itanium was it didn't just rely on "the compiler" instead it relied on the mystical "sufficiently smart compiler" (that never materialised).</p>
</div>2023-02-04T22:27:59ZBy Chris Siebenmann on /blog/tech/TwoRISCStoriestag:CSpace:blog/tech/TwoRISCStories:ca77c8993c32b6c99d11d48964287416e5bf002dChris Siebenmann<div class="wikitext"><p>Although I haven't examined Itanium's ISA in detail, my impression is
that it was a VLIW RISC architecture in that the actual instructions
were wide but the individual sub-instructions within them were RISCy,
and the whole thing had a RISCy approach where it depended very much on
compilers instead of in-CPU scheduling and so on.</p>
<p>(Based on some web searches, it also seems that the general impression
of Itanium is that it falls into the RISC family.)</p>
</div>2013-05-02T15:37:07ZFrom 76.113.49.212 on /blog/tech/TwoRISCStoriestag:CSpace:blog/tech/TwoRISCStories:fa36593753dde79a47c2bee4d016395f1aca1e70From 76.113.49.212<div class="wikitext"><p>Itanium was not a RISC. It's a complex ISA that primarily aims at parallel execution, or using the large available gate count for something smarter than enormous cache.</p>
</div>2013-05-01T20:59:33ZFrom 71.223.255.114 on /blog/tech/TwoRISCStoriestag:CSpace:blog/tech/TwoRISCStories:17e70ac27cae086f4ed993e146ed3d60e0b655d5From 71.223.255.114<div class="wikitext"><p>It's a shame that the SPARC T1 and T2 didn't make more of a hit with the design being open source. I know there's a couple FPGA's out there with a T1 design. </p>
<p>-Kevin</p>
</div>2013-05-01T05:16:11Z